FIG. 1 shows a depiction of a prior art floating gate field effect transistor (FET). The floating gate transistor depicted in FIG. 1 includes a semiconductor substrate 101 having source 108 and drain 109 regions. Above the semiconductor substrate are: 1) a source electrode/contact 106 made of metal; 2) a drain electrode/contact 107 made of metal; and, 3) a multilayer gate structure that includes an electrically conductive “control” gate electrode 105 and an electrically conductive “floating” gate electrode 103 that is sandwiched between dielectric layers 102 and 104.
Being a field effect transistor, the amount of current that flows through the drain 107 and source 106 nodes (IDS) of the floating gate FET in response to a voltage applied across its drain 107 and source 106 nodes (VDS) is a function of the number of free carriers that are induced along a “channel” that resides along the surface of the semiconductor substrate 101 beneath the lower dielectric 102 of the gate structure. The number of free carriers that are induced in the channel is a function of the electrical state of the gate structure.
In particular, if the capacitor formed by the floating gate 103 and dielectric 102 layer is holding a large positive electrical charge (which corresponds to a larger positive voltage being held by the floating gate 103), more free electrons will be induced in the channel in response to an applied positive voltage at the control gate electrode 105 than if a small positive electrical charge were held by the capacitor and the same applied positive voltage were applied at the control gate electrode 105. That is, the amount of charge held by the capacitor formed by the floating gate electrode 103 and dielectric layer 102 affects the threshold or “turn-on” voltage of the device.
Because the capacitor formed by the floating gate 103 and dielectric layer 102 can hold charge for long periods of time without the application of an external electrical voltage source, floating gate transistors have been used to effect non volatile semiconductor memory storage cells. Specifically, different device thresholds effected with different charge levels held by the capacitance between the floating gate electrode 103 and the channel are used to represent whether the transistor is holding a logical 0 or a logical 1.
For instance, in the case of an n-type channel, a higher positive voltage applied to the control gate electrode 105 results in more positive charge being held by the floating gate electrode capacitor; which, in turn, results in a lower threshold device (which is easier to place into active mode). By contrast, a lower positive voltage applied to the control gate electrode 105 results in less positive charge being held by the floating gate electrode; which, in turn, results in a higher threshold device (which is harder to place in active mode). Furthermore, for a fixed applied VDS voltage, a lower threshold voltage essentially corresponds to more IDS current for a given voltage applied to the control gate electrode 105 than if the device had a higher threshold voltage.
These concepts permit a memory cell to be implemented where a first logic state (e.g., a 1) is written by applying a control gate voltage that sets the device at a first threshold level (e.g., a lower threshold level) and a second logic state (e.g., a 0) is written by applying a control gate voltage that sets the device at a second threshold level (e.g., a higher threshold level). If the device is always read with the same control gate voltage and VDS voltage, the device will exhibit different IDS currents depending on what logic state it is in (e.g., more IDS current if it has a lower threshold voltage, less IDS current if it has a higher threshold voltage).
FIG. 2 illustrates a naturally occurring hysteresis loop 200 that helps illustrate the behavior graphically. If the device was written as a “1” with a higher control gate voltage VCG_1 that established a lower threshold, when the device is later read with a control gate voltage VR, it will exhibit a higher IDS current (point A along leg 201) than if the device had been written as a “0” with a lower control gate voltage VCG_2 that established a higher threshold (IDS current point B along leg 202).
A problem with non volatile floating gate memory cell memories, however, is that the continued shrinking of them to improve their storage densities results in a thinning of dielectric layer 102. As dielectric layer 102 is made thinner and thinner, the capacitor formed with the floating gate electrode 103 and layer 102 begins to leak more and more current; which, in turn, corresponds to an inability of the device to hold the threshold level it is expected to sustain over long periods of time without electrical power being applied.